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s-8204b series www.sii-ic.com battery protection ic for 3-series or 4-series cell pack ? seiko instruments inc., 2008-2013 rev.3.6 _00 seiko instruments inc. 1 the s-8204b series includes high-accuracy voltage detection circuits and delay circuits, in single use, makes it possible for users to monitor the status of 3-series or 4-series cell lithium-ion rechargeable battery. by switching the voltage level which is applied to the sel pin, users are able to use the s-82 04b series either for 3-series or 4-series cell pack. by cascade connection using the s-8204b series, it is also possible to protect 6-series or more cells *1 lithium-ion rechargeable battery pack. *1. refer to the application note for connection exampl es of protection circuit for 6-series or more cells. in case of protecting 5-series cell lithium-ion re chargeable battery pack, contact our sales office. ? features ? high-accuracy voltage detection function for each cell overcharge detection voltage n (n = 1 to 4) 3.65 v to 4.6 v (50 mv step) accuracy 25 mv overcharge release voltage n (n = 1 to 4) 3.5 v to 4.6 v *1 accuracy 50 mv overdischarge detection voltage n (n = 1 to 4) 2.0 v to 3.0 v (100 mv step) accuracy 80 mv overdischarge release voltage n (n = 1 to 4) 2.0 v to 3.4 v *2 accuracy 100 mv ? discharge overcurrent detection in 3-step discharge overcurrent detection voltage 1 0. 05 v to 0.30 v (50 mv step) accuracy 15 mv discharge overcurrent detection volt age 2 0.5 v (fixed) accuracy 100 mv load short-circuit detection voltage 1.0 v (fixed) accuracy 300 mv ? settable by external capacitor; overcharge detection del ay time, overdischarge detection delay time, discharge overcurrent detection delay time 1, discharge overcurrent detection delay time 2 (load short-circuit detection delay time is internally fixed.) ? switchable between 3-series and 4-series cell by using the sel pin ? independent charge and discharge control by the control pins ? high-withstand voltage element absolute maximum rating: 24 v ? wide operation voltage range 2 v to 22 v ? wide operation temperature range ta = ? 40c to + 85c ? low current consumption during operation 33 a max. (ta = + 25c) during power-down 0.1 a max. (ta = + 25c) ? lead-free, sn 100%, halogen-free *3 *1. overcharge hysteresis voltage n (n = 1 to 4) is sele ctable in 0 v, or in 0.1 v to 0.4 v in 50 mv step. (overcharge hysteresis volt age = overcharge detection voltage ? overcharge release voltage) *2. overdischarge hysteresis voltage n (n = 1 to 4) is sele ctable in 0 v, or in 0.2 v to 0.7 v in 100 mv step. (overdischarge hysteresis volt age = overdischarge release voltage ? overdischarge detection voltage) *3. refer to " ? product name structure " for details. ? application ? rechargeable lithium-ion battery pack ? package ? 16-pin tssop
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 2 ? block diagram cop vmp dop + ? vini discharge overcurrent 1 cdt cct cit vss control circuit r vmd r vms vdd vc1 vc2 vc3 vc4 ctlc ctld overcharge 1 sel delay circuit + ? + ? ? + + ? + ? + ? + ? ? + ? + ? + delay circuit delay circuit delay circuit over- discharge 1 overcharge 2 over- discharge 2 overcharge 3 over- discharge 3 overcharge 4 over- discharge 4 discharge overcurrent 2 load short circuit delay circuit remark diodes in the figure are parasitic diodes. figure 1
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 3 ? product name structure 1. product name s-8204b xx - xxxx x environmental code u: lead-free (sn 100%), halogen-free s: lead-free, halogen-free package name (abbreviation) and packing specifications *1 tct1: 16-pin tssop, tape serial code *2 sequentially set from aa to zz *1. refer to the tape drawing. *2. refer to " 3. product name list ". 2. package table 1 package drawing codes package name dimension tape reel environmental code = s ft016-a-p- sd ft016-a-c-sd ft016-a-r-sd 16-pin tssop environmental code = u ft016-a-p- sd ft016-a-c-sd ft016-a-r-s1
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 4 3. product name list table 2 product name overcharge detection voltage [v cu ] overcharge release voltage [v cl ] overdischarge detection voltage [v dl ] overdischarge release voltage [v du ] discharge overcurrent detection voltage 1 [v diov1 ] 0 v battery charge function power-down function S-8204BAB-TCT1Y 4.350 v 4.150 v 2.00 v 2.70 v 0.250 v available available s-8204bac-tct1y 4.225 v 4.075 v 2.30 v 3.00 v 0.100 v available available s-8204bad-tct1y 3.800 v 3.600 v 2.00 v 2.30 v 0.300 v available available s-8204bae-tct1y 4.350 v 4.150 v 2.50 v 3.00 v 0.250 v available available s-8204baf-tct1y 4.350 v 4.150 v 2.30 v 3.00 v 0.100 v available available s-8204bag-tct1y 4.350 v 4.150 v 2.80 v 3.30 v 0.100 v available available s-8204bah-tct1y 4.200 v 4.000 v 2.60 v 3.00 v 0.100 v available available s-8204bai-tct1y 3.900 v 3.800 v 2.00 v 2.00 v 0.150 v unavailable available s-8204baj-tct1y 4.300 v 4.100 v 2.50 v 2.90 v 0.250 v available available s-8204bak-tct1y 3.650 v 3.500 v 2.40 v 3.00 v 0.100 v available available s-8204bal-tct1y 4.200 v 4.100 v 2.70 v 2.90 v 0.250 v available available s-8204bam-tct1y 4.400 v 4.200 v 2.00 v 2.70 v 0.250 v available available s-8204ban-tct1y 4.100 v 4.100 v 2.00 v 2.50 v 0.150 v unavailable available s-8204bao-tct1y 3.900 v 3.600 v 2.50 v 2.70 v 0.100 v unavailable available s-8204bap-tct1y 4.320 v 4.120 v 2.40 v 3. 00 v 0.100 v unavailable available s-8204baq-tct1y 3.800 v 3.600 v 2.00 v 2.30 v 0.150 v available available s-8204bar-tct1y 3.850 v 3.650 v 2.50 v 2.70 v 0.150 v available available s-8204bas-tct1y 4.250 v 4.150 v 2.80 v 3.00 v 0.150 v available available s-8204bat-tct1y 3.650 v 3.500 v 2.00 v 2.70 v 0.100 v available available s-8204bau-tct1y 4.200 v 4.100 v 2.70 v 2.90 v 0.100 v available available s-8204bav-tct1y 3.900 v 3.600 v 2.00 v 2.70 v 0.100 v available available s-8204baw-tct1y 3.800 v 3.650 v 2.20 v 2.50 v 0.100 v available available s-8204bax-tct1y 4.250 v 4.250 v 2.00 v 2.00 v 0.100 v unavailable available s-8204bay-tct1y 3.900 v 3.600 v 2.30 v 2.50 v 0.100 v available available s-8204baz-tct1y 4.250 v 4.100 v 3.00 v 3.30 v 0.100 v available available s-8204bba-tct1y 4.250 v 4.150 v 2.50 v 3.00 v 0.100 v available available s-8204bbb-tct1y 4.250 v 4.150 v 2.70 v 3.00 v 0.250 v unavailable available s-8204bbc-tct1y 4.250 v 4.100 v 2.80 v 3.20 v 0.250 v unavailable available s-8204bbd-tct1y 4.300 v 4.200 v 2.30 v 3.00 v 0.100 v available available s-8204bbe-tct1y 3.800 v 3.600 v 2.00 v 2.30 v 0.100 v available available s-8204bbf-tct1y 3.800 v 3.600 v 2.00 v 2.30 v 0.050 v available available s-8204bbg-tct1y 4.250 v 4.100 v 2.80 v 3.30 v 0.100 v unavailable available s-8204bbh-tct1y 4.250 v 4.150 v 2.70 v 3.00 v 0.125 v unavailable available s-8204bbi-tct1u 4.250 v 4.150 v 2.70 v 3.00 v 0.125 v unavailable unavailable s-8204bbj-tct1u 4.250 v 4.150 v 2.70 v 3.00 v 0.150 v unavailable unavailable s-8204bbk-tct1u 4.250 v 4.190 v 2.80 v 3.00 v 0.150 v available available s-8204bbl-tct1u 4.230 v 4.230 v 2.80 v 3.00 v 0.150 v available available remark 1. please contact our sales office for products with detec tion voltage values other than those specified above. 2. y: s or u 3. please select products of environmental code = u for sn 100%, halogen-free products.
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 5 ? pin configuration 1. 16-pin tssop 5 4 6 8 7 2 3 1 12 13 11 9 10 15 14 16 top view figure 2 table 3 pin no. symbol description 1 cop connection pin of charge control fet gate (pch open-drain output) 2 vmp voltage detection pin between vdd pin and vmp pin 3 dop connection pin of discharge control fet gate (cmos output) 4 vini voltage detection pin between vss pin and vini pin, discharge overcurrent 1 / 2 detection pin, load short-circuit detection pin 5 cdt capacitor connection pin for delay for overdischarge detection 6 cct capacitor connection pin for delay for overcharge detection 7 cit capacitor connection pin for delay for discharge overcurrent 1 / 2 8 sel pin for switching 3-series or 4-series cell ? v ss level: 3-series cell ? v dd level: 4-series cell 9 vss input pin for negative power supply, connection pin for negative voltage of battery 4 10 vc4 connection pin for negative voltage of battery 3, connection pin for positive voltage of battery 4 11 vc3 connection pin for negative voltage of battery 2, connection pin for positive voltage of battery 3 12 vc2 connection pin for negative voltage of battery 1, connection pin for positive voltage of battery 2 13 vc1 connection pin for positive voltage of battery 1 14 vdd input pin for positive power supply, connection pin for positive voltage of battery 1 15 ctld discharge fet control pin 16 ctlc charge fet control pin
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 6 ? absolute maximum ratings table 4 (ta = + 25 c unless otherwise specified) item symbol applied pin absolute maximum rating unit input voltage between vdd pin and vss pin v ds ? v ss ? 0.3 to v ss + 24 v input pin voltage v in vc1, vc2, vc3, vc4, ctlc, ctld, sel, cct, cdt, cit, vini v ss ? 0.3 to v dd + 0.3 v vmp pin input voltage v vmp vmp v ss ? 0.3 to v ss + 24 v dop pin output voltage v dop dop v ss ? 0.3 to v dd + 0.3 v cop pin output voltage v cop cop v dd ? 24 to v dd + 0.3 v power dissipation p d ? 1100 *1 mw operation ambient temperature t opr ? ? 40 to + 85 c storage temperature t stg ? ? 40 to + 125 c *1. when mounted on board [mounted board] (1) board size: 114.3 mm 76.2 mm t1.6 mm (2) board name: jedec standard51-7 caution the absolute maximum ratings are rated values exceeding which the product could suffer physica l damage. these values must therefore not be exceeded under any conditions. 0 50 100 150 800 400 0 power dissipation (p d ) [mw] ambient temperature (ta) [ c] 1000 600 200 1200 figure 3 power dissipation of package (when mounted on board)
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 7 ? electrical characteristics table 5 (1 / 2) (ta = + 25 c unless otherwise specified) item symbol condition min. typ. max. unit test circuit detection voltage overcharge detection voltage n (n = 1, 2, 3, 4) v cun 3.65 v to 4.6 v, adjustable, 50 mv step v cun ? 0.025 v cun v cun + 0.025 v 2 v cl v cu v cln ? 0.05 v cln v cln + 0.05 v 2 overcharge release voltage n (n = 1, 2, 3, 4) v cln 3.5 v to 4.6 v, adjustable, 50 mv step v cl = v cu v cln ? 0.025 v cln v cln + 0.025 v 2 overdischarge detection voltage n (n = 1, 2, 3, 4) v dln 2.0 v to 3.0 v, adjustable, 100 mv step v dln ? 0.08 v dln v dln + 0.08 v 2 v dl v du v dun ? 0.10 v dun v dun + 0.10 v 2 overdischarge release voltage n (n = 1, 2, 3, 4) v dun 2.0 v to 3.4 v, adjustable, 100 mv step v dl = v du v dun ? 0.08 v dun v dun + 0.08 v 2 discharge overcurrent detection voltage 1 v diov1 0.05 v to 0.30 v, adjustable v diov1 ? 0.015 v diov1 v diov1 + 0.015 v 2 discharge overcurrent detection voltage 2 v diov2 ? 0.4 0.5 0.6 v 2 load short-circuit detection voltage v short ? 0.7 1.0 1.3 v 2 temperature coefficient 1 *1 t coe1 ta = 0c to 50c *3 ? 1.0 0 1.0 mv/c 2 temperature coefficient 2 *2 t coe2 ta = 0c to 50c *3 ? 0.5 0 0.5 mv/c 2 delay time function *4 cct pin internal resistance r inc v1 = 4.7 v, v2 = v3 = v4 = 3.5 v 6.15 8.31 10.2 m 3 cdt pin internal resistance r ind v1 = 1.5 v, v2 = v3 = v4 = 3.5 v 615 831 1020 k 3 cit pin internal resistance 1 r ini1 v1 = v2 = v3 = v4 = 3.5 v 123 166 204 k 3 cit pin internal resistance 2 r ini2 v1 = v2 = v3 = v4 = 3.5 v 12.3 16.6 20.4 k 3 cct pin detection voltage v cct v ds = 15.2 v, v1 = 4.7 v, v2 = v3 = v4 = 3.5 v v ds 0.68 v ds 0.70 v ds 0.72 v 3 cdt pin detection voltage v cdt v ds = 12.0 v, v1 = 1.5 v, v2 = v3 = v4 = 3.5 v v ds 0.68 v ds 0.70 v ds 0.72 v 3 cit pin detection voltage v cit v ds = 14.0 v, v1 = v2 = v3 = v4 = 3.5 v v ds 0.68 v ds 0.70 v ds 0.72 v 3 load short-circuit detection delay time t short fet gate capacitance = 2000 pf 100 300 600 s 3 0 v battery charge function 0 v battery charge starting voltage v 0cha 0 v battery charge function "available" ? 1.2 2.0 v 2 0 v battery charge inhibition battery voltage v 0inh 0 v battery charge function "unavailable" 0.4 0.7 1.1 v 2 internal resistance resistance between vmp pin and vdd pin r vmd ? 0.5 1 1.5 m 4 resistance between vmp pin and vss pin r vms with power-down function 450 900 1800 k 4
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 8 table 5 (2 / 2) (ta = + 25 c unless otherwise specified) item symbol condition min. typ. max. unit test circuit input voltage operation voltage between vdd pin and vss pin v dsop fixed output voltage of dop pin and cop pin 2 ? 22 v 2 ctlc pin input voltage "h" v ctlch v1 = v2 = v3 = v4 = 3.5 v ? ? 13.2 v 2 ctlc pin input voltage "l" v ctlcl v1 = v2 = v3 = v4 = 3.5 v 10.1 ? ? v 2 ctld pin input voltage "h" v ctldh v1 = v2 = v3 = v4 = 3.5 v ? ? 13.2 v 2 ctld pin input voltage "l" v ctldl v1 = v2 = v3 = v4 = 3.5 v 10.1 ? ? v 2 sel pin input voltage "h" v selh v ds = 14.0 v, v1 = v2 = v3 = v4 = 3.5 v v ds 0.8 ? ? v 2 sel pin input voltage "l" v sell v ds = 14.0 v, v1 = v2 = v3 = v4 = 3.5 v ? ? v ds 0.2 v 2 input current current consumption during operation i ope v1 = v2 = v3 = v4 = 3.5 v ? 15 33 a 1 current consumption during power-down i pdn with power-down function, v1 = v2 = v3 = v4 = 1.5 v ? ? 0.1 a 1 current consumption during overdischarge i oped without power-down function, v1 = v2 = v3 = v4 = 1.5 v ? 14 32 a 1 vc1 pin current i vc1 v1 = v2 = v3 = v4 = 3.5 v 0.5 1.5 3.0 a 4 vc2 pin current i vc2 v1 = v2 = v3 = v4 = 3.5 v ? 0.3 0 0.3 a 4 vc3 pin current i vc3 v1 = v2 = v3 = v4 = 3.5 v ? 0.3 0 0.3 a 4 vc4 pin current i vc4 v1 = v2 = v3 = v4 = 3.5 v ? 0.3 0 0.3 a 4 ctlc pin current "h" i ctlch v1 = v2 = v3 = v4 = 3.5 v, v ctlc = v dd 0.4 0.6 0.8 a 4 ctlc pin current "l" i ctlcl v1 = v2 = v3 = v4 = 3.5 v, maximum current flowing from ctlc pin ? 20.0 ? 10.0 ? 3.0 a 4 ctld pin current "h" i ctldh v1 = v2 = v3 = v4 = 3.5 v, v ctld = v dd 0.4 0.6 0.8 a 4 ctld pin current "l" i ctldl v1 = v2 = v3 = v4 = 3.5 v, maximum current flowing from ctld pin ? 20.0 ? 10.0 ? 3.0 a 4 sel pin current "h" i selh v1 = v2 = v3 = v4 = 3.5 v, v sel = v dd ? ? 0.1 a 4 sel pin current "l" i sell v1 = v2 = v3 = v4 = 3.5 v, v sel = v ss ? 0.1 ? ? a 4 output current cop pin source current i coh v cop = v dd ? 0.5 v 10 ? ? a 4 cop pin leakage current i col v cop = 0 v ? ? 0.1 a 4 dop pin source current i doh v dop = v dd ? 0.5 v 10 ? ? a 4 dop pin sink current i dol v dop = v ss + 0.5 v 10 ? ? a 4 *1. voltage temperature coefficient 1: overcharge detection voltage *2. voltage temperature coefficient 2: discharge overcurrent detection voltage 1 *3. since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production. *4. delay time function is described in " ? operation " in detail.
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 9 ? test circuit this chapter describes how to test the s-8204b series. in case of selecting to use it for 4-series cell battery, set sel pin = v dd . for 3-series cell battery, set sel pin = v ss and short between the vc4 pin and the vss pin. 1. current consumption during operation and power-down (test circuit 1) 1. 1 current consumption during operation (i ope ) the current at the vss pin when v1 = v2 = v3 = v4 = 3.5 v and v vmp = v dd is the current consumption during operation (i ope ). 1. 2 current consumption during power-down (i pdn ) (with power-down function) the current at the vss pin when v1 = v2 = v3 = v4 = 1.5 v and v vmp = v ss is the current consumption during power-down (i pdn ). 1. 3 current consumption during overdischarge (i oped ) (without power-down function) the current at the vss pin when v1 = v2 = v3 = v4 = 1.5 v and v vmp = v ss is the current consumption during overdischarge (i oped ). 2. overcharge detection voltage, overcharge release voltage, overdischarge detection voltage, overdischarge release voltage, discharge overcurre nt detection voltage 1, discharge overcurrent detection voltage 2, load short-circuit detection voltage, ctlc pin input voltage "h", ctlc pin input voltage "l", ctld pin input voltage "h", ct ld pin input voltage "l", sel pin input voltage "h", sel pin input voltage "l" (test circuit 2) confirm both the cop pin and the dop pin are in "h" (its voltage level is v ds 0.9 v or more) after setting v vmp = v sel = v ctlc = v ctld = v dd , v vini = v ss , cct pin = open, cdt pin = open, cit pin = open, v1 = v2 = v3 = v4 = 3.5 v. (this status is referred to as initial status.) 2. 1 overcharge detection voltage (v cu1 ), overcharge release voltage (v cl1 ) the overcharge detection voltage (v cu1 ) is a voltage at v1; when the cop pin's voltage is set to "l" (its voltage level is v dd 0.1 v or less) after increasing a voltage at v1 gradually from the initial status. after that, decreasing a voltage at v1 gradually, a voltage at v1 when the cop pin's voltage is set to "h"; is the overcharge release voltage (v cl1 ). 2. 2 overdischarge detection voltage (v dl1 ), overdischarge release voltage (v du1 ) the overdischarge detection voltage (v dl1 ) is a voltage at v1; when the dop pin's voltage is set to "l" after decreasing a voltage at v1 gradually from the initial status. after that, increasing a voltage at v1 gradually, a voltage at v1 when the dop pin?s voltage is set to "h"; is the overdischarge release voltage (v du1 ). by changing the voltage at vn (n = 2 to 4), users can define the overcharge detection voltage (v cun ), the overcharge release voltage (v cln ), the overdischarge detection voltage (v dln ), the overdischarge release voltage (v dun ) as well when n = 1. 2. 3 discharge overcurrent detection voltage 1 (v diov1 ) the discharge overcurrent detection voltage 1 (v diov1 ) is the vini pin's voltage; when the dop pin's voltage is set to "l" after increasing the vini pin?s voltage gradually from the initial status. 2. 4 discharge overcurrent detection voltage 2 (v diov2 ) the discharge overcurrent detection voltage 2 (v diov2 ) is a voltage at the vini pin; when a flowing current from the cit pin reaches 500 a or more after increasing the vini pin's voltage gradually from the initial status. 2. 5 load short-circuit detection voltage (v short ) the load short-circuit detection voltage (v short ) is the vini pin's voltage; when the dop pin's voltage is set to "l" after increasing the vini pin's voltage gradually after setting the cit pin's voltage v ss level from the initial status.
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 10 2. 6 ctlc pin input voltage "h" (v ctlch ), ctlc pin input voltage "l" (v ctlcl ) the ctlc pin input voltage "l" (v ctlcl ) is the ctlc pin's voltage; when the cop pin's voltage is set to "l" after decreasing the ctlc pin's voltage gradually from the initial status. after that, increasing the ctlc pin's voltage gradually, the ctlc pin's voltage when the cop pin's voltage is set to "h"; is the ctlc pin input voltage "h" (v ctlch ). 2. 7 ctld pin input voltage "h" (v ctldh ), ctld pin input voltage "l" (v ctldl ) the ctld pin input voltage "l" (v ctldl ) is the ctld pin's voltage; when the dop pin's voltage is set to "l" after decreasing the ctld pin's voltage gradually from the initial status. after that, increasing the ctld pin's voltage gradually, the ctld pin's voltage when the dop pin's voltage is set to "h"; is the ctld pin input voltage "h" (v ctldh ). 2. 8 sel pin input voltage "h" (v selh ), sel pin input voltage "l" (v sell ) start from the initial status, set v4 = 0 v. confirm the dop pin is in "l". after that, decreasing the sel pin's voltage gradually, the sel pin's voltage when the dop pin's voltage is set to "h"; is the sel pin input voltage "l" (v sell ). after that, increasing the sel pin's voltage gradually, the sel pin's voltage when the dop pin's voltage is set to "l"; is the sel pin input voltage "h" (v selh ). 3. cct pin internal resistance, cdt pin internal re sistance, cit pin internal resistance 1, cit pin internal resistance 2, cct pin detection voltage, cdt pin detection voltage, cit pin detection voltage, load short-circuit detection delay time (test circuit 3) confirm both the cop pin and the dop pin are in "h" (its voltage level is v ds 0.9 v or more) after setting v vmp = v sel = v ctlc = v ctld = v dd , v vini = cct = cdt = cit = v ss , v1 = v2 = v3 = v4 = 3.5 v. (this status is referred to as initial status.) 3. 1 cct pin internal resistance (r inc ) the cct pin internal resistance (r inc ) is r inc = v ds / i cct , i cct is the current which flows from the cct pin when setting v1 = 4.7 v from the initial status. 3. 2 cdt pin internal resistance (r ind ) the cdt pin internal resistance (r ind ) is r ind = v ds / i cdt , i cdt is the current which flows from the cdt pin when setting v1 = 1.5 v from the initial status. 3. 3 cit pin internal resistance 1 (r ini1 ) the cit pin internal resistance 1 (r ini1 ) is r ini1 = v ds / i cit1 , i cit1 is the current which flows from the cit pin when setting v vini = v diov1 max. + 0.05 v from the initial status. 3. 4 cit pin internal resistance 2 (r ini2 ) the cit pin internal resistance 2 (r ini2 ) is r ini2 = v ds / i cit2 , i cit2 is the current which flows from the cit pin when setting v vini = v diov2 max . + 0.05 v from the initial status. 3. 5 cct pin detection voltage (v cct ) the cct pin detection voltage (v cct ) is the voltage at the cct pin when the cop pin's voltage is set to "l" (voltage v ds 0.1 v or less) after increasing the cct pin's voltage gradually, after setting v1 = 4.7 v from the initial status. 3. 6 cdt pin detection voltage (v cdt ) the cdt pin detection voltage (v cdt ) is the voltage at the cdt pin when the dop pin's voltage is set to "l" (voltage v ds 0.1 v or less) after increasing the cdt pin's voltage gradually, after setting v1 = 1.5 v from the initial status.
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 11 3. 7 cit pin detection voltage (v cit ) the cit pin detection voltage (v cit ) is the voltage at the cit pin when the dop pin's voltage is set to "l" (voltage v ds 0.1 v or less) after increasing the cit pin's voltage gradually, after setting v vini = v diov1 max. + 0.05 v from the initial status. 3. 8 load short-circuit detection delay time (t short ) load short-circuit detection delay time (t short ) is a period in which the vini pin's voltage changes from "h" to "l" by changing the vini pin's voltage instantaneously from the initial status to v short max. + 0.05 v. 4. 0 v battery charge starting voltage (0 v battery charge function "available"), 0 v battery charge inhibition battery voltage (0 v batt ery charge function "unavailable") (test circuit 2) confirm both cop pin and dop pin are in "h" (its voltage level is v ds 0.9 v or more) after setting v vmp = v sel = v ctlc = v ctld = v dd , v vini = v ss , cct pin = open, cdt pin = open, cit pin = open, v1 = v2 = v3 = v4 = 3.5 v. (this status is referred to as initial status.) according to user's selection of the function to charge 0 v battery, either function of voltage for start charging 0 v battery or battery voltage for inhibit charging 0 v battery is applied to each product. 4. 1 0 v battery charge starting voltage (v 0cha ) ( 0 v battery charge function "available") 0 v battery charge starting voltage (v 0cha ) is a voltage at v1; when a voltage at the cop pin is set to "h" after increasing a voltage at v1 gradually, after setting v1 = v2 = v3 = v4 = 0 v from the initial status. 4. 2 0 v battery charge inhibition battery voltage (v 0inh ) (0 v battery charge function "unavailable") 0 v battery charge inhibition battery voltage (v 0inh ) is a voltage at v1; when a voltage at the cop pin is set to "l" after decreasing a voltage at v1 gradually from the initial status. 5. resistance between vmp pin and vdd pin, resistance between vmp pin and vss pin, vc1 pin current, vc2 pin current, vc3 pin current, vc4 pi n current, ctlc pin current "h", ctlc pin current "l", ctld pin current "h", ctld pin cu rrent "l", sel pin current "h", sel pin current "l", cop pin source current, cop pin leakage current, dop pin source current, dop pin sink current (test circuit 4) set v ctlc = v ctld = v vmp = v sel = v dd , v vini = v ss , v1 = v2 = v3 = v4 = 3.5 v, set other pins open. (this status is referred to as initial status.) 5. 1 resistance between vmp pin and vdd pin (r vmd ) the value of resistance between vmp pin and vdd pin (r vmd ) can be defined by r vmd = v ds / i vmd by using the vmp pin's current (i vmd ) when v vini = 1.5 v and v vmp = v ss after the initial status. 5. 2 resistance between vmp pin and vss pin (r vms ) the value of resistance between vmp pin and vss pin (r vms ) can be defined by r vms = v ds / i vms by using the vmp pin's current (i vms ) when v1 = v2 = v3 = v4 = 1.8 v after the initial status. 5. 3 vc1 pin current (i vc1 ), vc2 pin current (i vc2 ), vc3 pin current (i vc3 ), vc4 pin current (i vc4 ) in the initial status, each current flows in the vc1 pin, vc2 pin, vc3 pin, vc4 pin is the vc1 pin current (i vc1 ), the vc2 pin current (i vc2 ), the vc3 pin current (i vc3 ), the vc4 pin current (i vc4 ), respectively. 5. 4 ctlc pin current "h" (i ctlch ), ctlc pin current "l" (i ctlcl ) in the initial status, a current which flows in the ctlc pin is the ctlc pin current "h" (i ctlch ). after that, decreasing a voltage at the ctlc pin gradually, the maximum current which flows in the ctlc pin is; the ctlc pin current "l" (i ctlcl ).
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 12 5. 5 ctld pin current "h" (i ctldh ), ctld pin current "l" (i ctldl ) in the initial status, a current which flows in the ctld pin is the ctld pin current "h" (i ctldh ). after that, decreasing a voltage at the ctld pin gradually, the maximum current which flows in the ctld pin is; the ctld pin current "l" (i ctldl ). 5. 6 sel pin current "h" (i selh ), sel pin current "l" (i sell ) in the initial status, a current which flows in the sel pin is the sel pin current "h" (i selh ). after that, a current which flows in the sel pin when setting v sel = v ss is; the sel pin current "l" (i sell ). 5. 7 cop pin source current (i coh ), cop pin leakage current (i col ) start from the initial status, set v cop = v dd ? 0.5 v, a current which flows in the cop pin is the cop pin source current (i coh ). after that, a current which flows in the cop pin when setting v1 = v2 = v3 = v4 = 5.5 v, v cop = v ss is; the cop pin leakage current (i col ). 5. 8 dop pin source current (i doh ), dop pin sink current (i dol ) start from the initial status, set v dop = v dd ? 0.5 v, a current which flows in the dop pin is the dop pin source current (i doh ). after that, a current which flows in the dop pin when setting v1 = v2 = v3 = v4 = 1.8 v, v dop = v ss + 0.5 v is; the dop pin sink current (i dol ).
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 13 c 1 = 0.1 f v1 v2 v4 v3 a 1cop 2vmp 3dop 4vini 5 cdt 6 cct 7cit 8 16 vdd 15 vc1 14 vc2 13 vc3 12 vc4 11 ctlc ctld vss 9 s-8204b sel 10 figure 4 test circuit 1 c 1 = 0.1 f v1 v2 v4 v3 v v 1cop 2vmp 3dop 4 vin i 5 cdt 6 cc t 7cit 8 16 vdd 15 vc1 14 vc2 13 vc3 12 vc4 11 ctlc ctld vss 9 s-8204b sel 10 a figure 5 test circuit 2 c 1 = 0.1 f v1 v2 v4 v3 1cop 2vmp 3dop 4vini 5 cdt 6 cct 7cit 8 16 vdd 15 vc1 14 vc2 13 vc3 12 vc4 11 ctlc ctld vss 9 s-8204b sel 10 v v a a a figure 6 test circuit 3
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 14 c 1 = 0.1 f v1 v2 v4 v3 a a a a a a a 1 cop 2 vmp 3 dop 4 vini 5 cdt 6 cct 7 cit 8 16 vdd 15 vc1 14 vc2 13 vc3 12 vc4 11 ctlc ctld vss 9 s-8204b sel 10 a a a figure 7 test circuit 4
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 15 ? operation remark refer to " ? connection examples of battery protection ic ". 1. normal status in the s-8204b series, both of the cop pin and the dop pin get the v dd level; when all values of battery voltage are in the range of overdischarge detection voltage (v dln ) to overcharge detection voltage (v cun ), and due to the discharge current, the vini pin's voltage is discharge overcurrent detection voltage (v diov1 ) or less. this is the normal status. at this time, the charge fet and discharge fet are on. 2. overcharge status in the s-8204b series, any voltage of the batteries increases to the level of v cun or more, the cop pin is set in high impedance. this is the overcharge status. the cop pin is pulled down to eb ? by an external resistor so that the charge fet is turned off and it stops charging. this overcharge status is released if eith er condition mentioned below is satisfied; (1) in case that the vmp pin voltage is 39 / 40 v ds or more; all voltages of the batteries are in the level of overcharge release voltage (v cln ) or less. (2) in case that the vmp pin voltage is 39 / 40 v ds or less; all voltages of the batteries are in the level of v cun or less. 3. overdischarge status in the s-8204b series, when any voltage of the batteries decreases to the level of v dln or less, the dop pin voltage gets the v ss level. this is the overdischarge status. the disc harge fet is turned off and it stops discharging. this overcharge status is released if eith er condition mentioned below is satisfied; (1) to release; the vmp pin voltage is in the v dd level or more, all voltages of the batteries are in the v dln level or more. (2) to release; the vmp pin voltage is v ds / 2 or more and the vmp pin voltage is in the v dd level or less, all voltages of the batteries are in the level of overdischarge release voltage (v dun ) or more. 4. power-down status in the s-8204b series, either the products with power-d own function or those without power-down function can be selected. 4. 1 with power-down function when the s-8204b series reaches the overdischarge status, the vmp pin is pulled down to the v ss level by a resistor between the vmp pin and the vss pin (r vms ). if the vmp pin voltage decreases to the level of v ds / 2 or less, almost every circuit in the s-8204b series stops working so that the current consumption decreases to the level of current consumption at power down (i pdn ) or less. this is the power-down status. the power-down status is released if the following condition is satisfied. (1) the vmp pin voltage gets v ds / 2 or more. 4. 2 without power-down function the vmp pin is not pulled down even when the s- 8204b series reaches the overdischarge status. the overdischarge status is maintained even if the vmp pin voltage decreases to the level of v ds / 2 or less, and the current consumption decreases to the level of current consumption during overdischarge (i oped ) or less.
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 16 5. discharge overcurrent status in the s-8204b series, in batteries in the normal status, the discharging current increases more than a certain value. as a result, if the status in which the vini pin voltage increases to the level of v diov1 or more, the dop pin gets the v ss level. this is the discharge overcurrent status. at this time, the discharge control fet is turned off and it stops discharging. the s-8204b series has three levels for discharge overcurrent detection (v diov1 , v diov2 , v short ). in the status of discharge overcurrent, the cop pin is set in high impedance. the vmp pin is pulled up to the v dd level by a resistor between the vmp pin and the vdd pin (r vmd ). the s-8204b series' operations against disc harge overcurrent detection voltage 2 (v diov2 ) and load short-circuit detection voltage (v short ) are as well in v diov1 . the discharge overcurrent status is released if the following condition is satisfied. (1) the vmp pin voltage gets v ds ? 1.2 v (typ.) or more. 6. 0 v battery charge function in the s-8204b series, regarding how to charge a discharged battery (0 v battery), users are able to select either function mentioned below. (1) allow to charge a 0 v battery (enable to charge a 0 v battery) a 0 v battery is charged when the volt age between the vdd pin and the vss pin (v ds ) is 0 v battery charge starting voltage (v 0cha ) or more. (2) inhibit charging a 0 v battery (unable to charge a 0 v battery) a 0 v battery is not charged when the battery voltage is 0 v battery charge inhibition battery voltage (v 0inh ) or less. caution when the vdd pin voltage is less than the minimum value of operation voltage between the vdd pin and the vss pin (v dsop ), the operation of the s-8204b series is not assured.
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 17 7. delay time setting in the s-8204b series, users are able to set delay time for the period; from detecting any voltage of the batteries or detecting changes in the voltage at the vini pin, to the output to the cop pin and the dop pin. each delay time is determined by a resistor in the s-8204b series and an external capacitor. in the overchage detection, when any voltage of the batteries gets v cun or more, the s-8204b series starts charging to the cct pin's capacitor (c cct ) via the cct pin's internal resistor (r inc ). after a certain period, the cop pin is set in high impedance if the voltage at the cct pin reaches the cct pin detection voltage (v cct ). this period is overcharge detection delay time (t cu ). t cu is calculated using the following equation (v ds = v1 + v2 + v3 + v4). t cu [s] = ? ln (1 ? v cct / v ds ) c cct [ f] r inc [m ] = ? ln (1 ? 0.7 (typ.)) c cct [ f] 8.31 [m ] (typ.) = 10.0 [m ] (typ.) c cct [ f] overdischarge detection delay time (t dl ), discharge overcurrent detection delay time 1 (t diov1 ), discharge overcurrent detection delay time 2 (t diov2 ) are calculated using the following equations as well. t dl [ms] = ? ln (1 ? v cdt / v ds ) c cdt [ f] r ind [k ] t diov1 [ms] = ? ln (1 ? v cit / v ds ) c cit [ f] r ini1 [k ] t diov2 [ms] = ? ln (1 ? v cit / v ds ) c cit [ f] r ini2 [k ] in case c cct = c cdt = c cit = 0.1 [ f], each delay time t cu , t dl , t diov1 , t diov2 is calculated as follows. t cu [s] = 10.0 [m ] (typ.) 0.1 [ f] = 1.0 [s] (typ.) t dl [ms] = 1000 [k ] (typ.) 0.1 [ f] = 100 [ms] (typ.) t diov1 [ms] = 200 [k ] (typ.) 0.1 [ f] = 20 [ms] (typ.) t diov2 [ms] = 20 [k ] (typ.) 0.1 [ f] = 2.0 [ms] (typ.) load short-circuit detection delay time (t short ) is fixed internally.
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 18 8. ctlc pin and ctld pin the s-8204b series has two pins to control. the ctlc pin controls the output voltage from the cop pin, the ctld pin controls the output voltage from the dop pin. thus it is possible for users to control the output voltages from the cop pin and dop pin independently. these controls precede the battery protection circuit. table 6 conditions set by ctlc pin ctlc pin cop pin "h" *1 normal status *4 open *2 "high-z" "l" *3 "high-z" *1. "h"; ctlc v ctlch *2. pulled down by i ctlch *3. "l"; ctlc v ctlcl *4. the status is controlled by the voltage detection circuit. table 7 conditions set by ctld pin ctld pin dop pin "h" *1 normal status *4 open *2 v ss level "l" *3 v ss level *1. "h"; ctld v ctldh *2. pulled down by i ctldh *3. "l"; ctld v ctldl *4. the status is controlled by the voltage detection circuit. caution note that when the power supply fluctuates, unexpected behavior might occur if an electrical potential is generated between the potentials of "h " level input to the ctlc pin / the ctld pin and ic's v dd by external filters r vdd1 and c vdd1 .
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 19 9. sel pin the s-8204b series has a pin to switch-control the protection for 3-cell or 4-cell battery. the overdischarge detection for v4-cell is inhibited by setting the sel pin "l", so that short-circuiting the v4 cell does not allow the overdischarge detection. this setting makes it possible to use the s-8204b series for 3-cell protection. the control by this sel pin precedes the battery protecti on circuit. be sure to use the sel pin in "h" or "l". table 8 conditions set by sel pin sel pin condition "h" *1 4-cell protection open indefinite "l" *2 3-cell protection *1. "h"; sel v selh *2. "l"; sel v sell in cascade connection, it is possible to use the s-8204b se ries for protecting 6-cell, 7-cell or 8-cell battery by combining the electrical level of the sel pin. table 9 conditions set by sel pin in cascade connection sel pin in s-8204b (1) sel pin in s-8204b (2) condition "l" *1 "l" *1 6-series cell protection "l" *1 "h" *2 7-series cell protection "h" *2 "h" *2 8-series cell protection *1. "l"; sel v sell *2. "h"; sel v selh
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 20 ? timing chart (circuit in figure 11) 1. overcharge detection and overdischarge detection (with power-down function) (n = 1 to 4) v cun v dln v cln battery voltage v eb- cop pin voltage dop pin voltage v ss charger connection load connection status *1 overcharge detection delay time (t cu ) overdischarge detection delay time (t dl ) (1) (2) (1) (3) (1) 39 / 40 v dd v ss vmp pin voltage 1 / 2 v dd v dd v dd high-z v dd (4) high-z (3) *1. (1): normal status (2): overcharge status (3): overdischarge status (4): power-down status remark the charger is assumed to charge with a constant current. v eb- indicates the open voltage of the charger. figure 8
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 21 2. overcharge detection and overdischarge detection (without power-down function) (n = 1 to 4) v cun v dln v cln battery voltage v eb- cop pin voltage dop pin voltage v ss charger connection load connection status *1 overcharge detection delay time (t cu ) overdischarge detection delay time (t dl ) (1) (2) (1) (1) 39 / 40 v dd v ss vmp pin voltage 1 / 2 v dd v dd v dd high-z v dd (3) *1. (1): normal status (2): overcharge status (3): overdischarge status remark the charger is assumed to charge with a constant current. v eb- indicates the open voltage of the charger. figure 9
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 22 3. discharge overcurrent detection v cun v dun v dln (n = 1 to 4 ) v cln battery voltage v hc v hd v dd dop pin voltage v ss high-z v dd v eb- cop pin voltage high-z high-z v dd v ss vmp pin voltage v short v diov2 v ini pin voltage v dd v diov1 load connection status *1 discharge overcurrent detecion delay time 1 (t diov1 ) (1) (2) (1) (1) discharge overcurrent detecion delay time 2 (t diov2 ) load short-circu it detecion delay time (t short ) (2) (1) (2) charger connection v ss *1. (1): normal status (2): discharge overcurrent status remark the charger is assumed to charge with a constant current. v eb- indicates the open voltage of the charger. figure 10
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 23 ? connection examples of battery protection ic 1. 4-series cell (with overcurrent protection function) r atl eb + eb? 1 cop 2 vmp 3 dop 4 vini 5 cdt 6 cct 7 cit 8 sel vc3 11 vc4 10 vss 9 vc2 12 vc1 13 vdd 14 ctld 15 ctlc 16 r sel c cdt c cct c vc1 c vc2 c vc3 c vc4 r vc4 r vc3 r vc2 r vc1 r vdd c vdd r cop nch fet1 (charge fet) nch fet2 (discharge fet) r dop r vini z d1 m1 m2 r vmp r eb ? c cit r sense s-8204b r ctlc r ctld figure 11
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 24 table 10 constants for external components (circuit in figure 11) symbol min. typ. max. unit r vc1 *1 0.51 1 1 k r vc2 *1 0.51 1 1 k r vc3 *1 0.51 1 1 k r vc4 *1 0.51 1 1 k r dop 2 5.1 10 k r cop 0.1 1 1 m r vmp 1 5.1 10 k r ctlc 1 1 10 k r ctld 1 1 10 k r vini 1 1 10 k r sel 1 1 100 k r vdd *1 22 47 100 c vc1 *1 0 47 100 nf c vc2 *1 0 47 100 nf c vc3 *1 0 47 100 nf c vc4 *1 0 47 100 nf c cct 0.01 0.1 ? f c cdt 0.01 0.1 ? f c vdd *1 0 1 2.2 f c cit ? 0.1 ? f r sense ? ? ? ? m1 ? ? ? ? m2 ? ? ? ? z d1 ? ? ? ? r eb ? ? 1 ? m r atl ? 20 ? m nch fet1 ? ? ? ? nch fet2 ? ? ? ? *1. set up a filter constant to be r vdd c vdd = 47 f ? or more, and to be r vc1 c vc1 = r vc2 c vc2 = r vc3 c vc3 = r vc4 c vc4 = r vdd c vdd . caution 1. the above constants may be changed without notice. 2. it is recommended that fi lter constants between the vdd pi n and the vss pin should be set to approximately 47 f ? . e.g., c vdd r vdd = 1.0 f 47 = 47 f ? sufficient evaluation of transient power supply fluctuation and overcurrent protection function with the actual application is needed to determine the proper constants. contact our sales office in case the constants should be set to other than 47 f ? . 3. it has not been confirmed whether the operation is normal in circuits other than the above example of connection. in addition, the example of connection shown above and the constants do not guarantee proper operation. perform thorough evaluation using an actual application to set the constant.
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 25 2. 7-series cell (cascade connection without overcurrent protection function) r vmp1 eb+ eb? 1cop 2vmp 3dop 4vini 5 cdt 6 cct 7cit 8sel vc3 11 vc4 10 vss 9 vc2 12 vc1 13 vdd 14 ctld 15 ctlc 16 r vini1 r sel1 r vdd1 r vc4 r vc3 r vc2 r vc1 1cop 2 vmp 3 dop 4 vini 5 cdt 6 cct 7 cit 8 sel vc3 11 vc4 10 vss 9 vc2 12 vc1 13 vdd 14 ctld 15 ctlc 16 r sel2 c cdt2 c cct2 r vmp2 r vini2 c vc3 c vdd1 c vc5 c vc6 c vc7 c vc8 r vc8 r vc7 r vc6 r vc5 r vdd2 c vdd2 r ctlc r ctld c cdt1 c cct1 r cit1 r cit2 r ifc r ifd d cop r cop charge fet c vc1 c vc2 discharge fet r dop s-8204b (1) s-8204b (2) figure 12 caution 1. it is recommended that filter constants between the vdd pin and the vss pin should be set to approximately 47 f ? . e.g., c vdd r vdd = 1.0 f 47 = 47 f ? sufficient evaluation of transient power supply fluctuation and overcurrent protection function with the actual application is needed to determine the proper constants. contact our sales office in case the constants should be set to other than 47 f ? . 2. it has not been confirmed whether the operation is normal in circuits other than the above example of connection. in addition, the example of connection shown above and the constants do not guarantee proper operation. perform thorough evaluation using an actual application to set the constant. remark refer to the application note for constants of each external component.
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 26 3. 8-series cell (cascade connection with overcurrent protection function) r atl eb+ eb? 1 cop 2 vmp 3dop 4 vini 5 cdt 6 cct 7 cit 8 sel vc3 11 vc4 10 vss 9 vc2 12 vc1 13 vdd 14 ctld 15 ctlc 16 r vini1 r sel1 r vdd1 r vc4 r vc3 r vc2 r vc1 1 cop 2 vmp 3 dop 4 vini 5 cdt 6 cct 7 cit 8 sel vc3 11 vc4 10 vss 9 vc2 12 vc1 13 vdd 14 ctld 15 ctlc 16 r sel2 c cdt2 c cct2 c vc3 c vdd1 c vc5 c vc6 c vc7 c vc8 r vc8 r vc7 r vc6 r vc5 r vdd2 c vdd2 r ctlc r ctld c cdt1 c cct1 r cit1 r ifc r ifd d cop r cop charge fet c vc1 c vc2 c vc4 discharge fet r dop r vini2 m1 m2 m4 r inv2 m3 r 1 r inv1 r eb ? c cit2 r sense s-8204b (1) s-8204b (2) r 2 z d1 figure 13 caution 1. it is recommended that filter constants between the vdd pin and the vss pin should be set to approximately 47 f ? . e.g., c vdd r vdd = 1.0 f 47 = 47 f ? sufficient evaluation of transient power supply fluctuation and overcurrent protection function with the actual application is needed to determine the proper constants. contact our sales office in case the constants should be set to other than 47 f ? . 2. it has not been confirmed whether the operation is normal in circuits other than the above example of connection. in addition, the example of connection shown above and the constants do not guarantee proper operation. perform thorough evaluation using an actual application to set the constant. remark refer to the application note for constants of each external component.
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 27 ? precautions ? the application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation. ? batteries can be connected in any order; however, ther e may be cases when dischargi ng cannot be performed when a battery is connected. in such a case, short the vmp pin and the vdd pin to return the ic to the normal mode. ? if both an overcharge battery and an overdischarge battery are included among the whole batteries, the condition is set in overcharge status and overdischarge status. ther efore either charging or discharging is impossible. ? do not apply an electrostatic discharge to this ic that exceeds the performance ratings of the built-in electrostatic protection circuit. ? sii claims no responsibility for any disputes arising out of or in connection with any infringement by products including this ic of patents owned by a third party.
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 28 ? characteristics (typical data) 1. current consumption 1. 1 i ope vs. v ds 1. 2 i ope vs. ta 01 5 2 0 i ope [a] 30 20 10 0 v ds [v] 40 52 2 25 15 5 35 10 ? 40 0 25 50 75 i ope [a] 30 20 10 0 ta [ c] 40 ?25 85 5 15 25 35 1. 3 i pdn vs. v ds 1. 4 i pdn vs. ta 01 5 2 0 i pdn [a] 0.06 0.04 0.02 0 v ds [v] 0.10 52 2 0.05 0.03 0.01 0.07 10 0.08 0.09 ? 40 0 25 50 75 i pdn [a] 0.06 0.04 0.02 0 ta [ c] 0.10 ?25 85 0.01 0.03 0.05 0.09 0.07 0.08 2. overcharge detection / release voltage, overdi scharge detection / release voltage, overcurrent detection voltage 2. 1 v cu vs. ta 2. 2 v cl vs. ta ? 40 0 25 50 75 v cu [v] 4.355 4.345 4.335 4.325 ta [ c] 4.375 ?25 85 4.330 4.340 4.350 4.370 4.360 4.365 ? 40 0 25 50 75 v cl [v] 4.16 4.14 4.12 4.10 ta [ c] 4.20 ?25 85 4.18 2. 3 v du vs. ta 2. 4 v dl vs. ta ? 40 0 25 50 75 v du [v] 2.72 2.68 2.64 2.60 ta [ c] 2.80 ?25 85 2.62 2.66 2.70 2.78 2.74 2.76 ? 40 0 25 50 75 v dl [v] 2.04 2.00 1.96 1.92 ta [ c] 2.08 ?25 85 1.94 1.98 2.02 2.06
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 29 2. 5 v diov1 vs. v ds 2. 6 v diov1 vs. ta 10 12 13 14 15 v diov1 [v] 0.27 0.25 0.23 0.21 v ds [v] 0.29 11 16 0.22 0.24 0.26 0.28 ? 40 0 25 50 75 v diov1 [v] 0.27 0.25 0.23 0.21 ta [ c] 0.29 ?25 85 0.22 0.24 0.26 0.28 2. 7 v diov2 vs. v ds 2. 8 v diov2 vs. ta 10 12 13 14 15 v diov2 [v] 0.54 0.50 0.46 0.42 v ds [v] 0.58 11 16 0.44 0.48 0.52 0.56 ? 40 0 25 50 75 v diov2 [v] 0.54 0.50 0.46 0.42 ta [ c] 0.58 ?25 85 0.44 0.48 0.52 0.56 2. 9 v short vs. v ds 2. 10 v short vs. ta 10 12 13 14 15 v short [v] 1.0 0.7 v ds [v] 1.3 11 16 0.8 0.9 1.1 1.2 ? 40 0 25 50 75 v short [v] 1.0 0.7 ta [ c] 1.3 ?25 85 0.8 0.9 1.1 1.2
battery protection ic for 3-series or 4-series cell pack s-8204b series rev.3.6 _00 seiko instruments inc. 30 3. cct pin internal resistance / detection voltage, cdt pin internal resistance / detection voltage, cit pin internal resistance / detection voltage and load short-circuit detection delay time 3. 1 r inc vs. ta 3. 2 v cct vs. ta (v ds = 15.2 v) ? 40 0 25 50 75 r inc [m ] 9.0 6.0 ta [ c] 12.0 ?25 85 7.0 8.0 10.0 11.0 ? 40 0 25 50 75 v cct [v] 10.7 10.4 ta [ c] 10.9 ?25 85 10.5 10.6 10.8 3. 3 r ind vs. ta 3. 4 v cdt vs. ta (v ds = 12.0 v) ? 40 0 25 50 75 r ind [k ] 900 600 ta [ c] 1200 ?25 85 700 800 1000 1100 ? 40 0 25 50 75 v cdt [v] 8.2 ta [ c] 8.6 ?25 85 8.3 8.4 8.5 3. 5 r ini1 vs. ta 3. 6 v cit vs. ta (v ds = 14.0 v) ? 40 0 25 50 75 r ini1 [k ] 180 120 ta [ c] 240 ?25 85 140 160 200 220 ? 40 0 25 50 75 v cit [v] 9.6 ta [ c] 10.0 ?25 85 9.7 9.8 9.9 3. 7 r ini2 vs. ta 3. 8 t short vs. ta ? 40 0 25 50 75 r ini2 [k ] 18.0 12.0 ta [ c] 24.0 ?25 85 14.0 16.0 20.0 22.0 ? 40 0 25 50 75 t short [s] 300 0 ta [ c] 600 ?25 85 100 200 400 500
battery protection ic for 3-series or 4-series cell pack rev.3.6 _00 s-8204b series seiko instruments inc. 31 4. cop pin / dop pin 4. 1 i coh vs. v cop 4. 2 i col vs. v cop 0 3.5 7 14 i coh [ma] 10 0 v cop [v] 20 10.5 15 5 25 0 5 10 20 i col [a] 0.07 0.05 0.03 0.00 v cop [v] 0.09 15 0.08 0.06 0.04 22 0.10 0.01 0.02 4. 3 i doh vs. v dop 4. 4 i dol vs. v dop 0 3.5 7 14 i doh [ma] 10 0 v dop [v] 20 10.5 15 5 25 0 1.8 3.6 7.2 i dol [ma] v dop [v] 5.4 3.5 2.5 1.5 0 4.5 4.0 3.0 2.0 5.0 0.5 1.0

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www.sii-ic.com ? the information described herein is subject to change without notice. ? seiko instruments inc. is not responsible for any pr oblems caused by circuits or diagrams described herein whose related industrial properties, patents, or ot her rights belong to third parties. the application circuit examples explain typical applications of the products, and do not guarant ee the success of any specific mass-production design. ? when the products described herein are regulated produ cts subject to the wassenaar arrangement or other agreements, they may not be exported without authoriz ation from the appropriate governmental authority. ? use of the information described he rein for other purposes and/or repr oduction or copying without the express permission of seiko instrum ents inc. is strictly prohibited. ? the products described herein cannot be used as par t of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equi pment, vehicle equipment, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment, without prior written permission of seiko instruments inc. ? the products described herein are not designed to be radiation-proof. ? although seiko instruments inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may oc cur. the user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.

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